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january 2008 rev 5 1/45 45 stpm11/12/13/14 single phase energy mete ring ic with pulsed output and digital calibration features ripple free active energy pulsed output direct stepper counter drivers shunt, current transformer, rogowsky coil sensors live and neutral monitoring (stpm13/14) easy and fast digital calibration at only one load point no-load, negative power and tamper indicators integrated linear vregs rc (stpm11/13) or crystal oscillator (stpm12/14) support 5060 hz - iec62052-11, iec62053- 2x specification less than 0.1% error description the stpm1x family is designed for effective measurement of active energy in a power line system using a rogowski coil, current transformer and shunt sensors. this device is specifically designed to provide all the necessary features to implement a single phase energy meter without any other active component. the stpm1x device family consists, essentially, of two parts: the analog part and the digital part. the former, is composed of a preamplifier and first order a/d converter blocks, band gap voltage reference, low drop voltage regulator. the digital part is composed of a s ystem control, oscillator, hard wired dsp and interface for calibration and configuration. the calibration and configuration are done by otp cells, that can be programmed through a serial interface. the configured bits are used for testing, configuration and calibration purposes. from two output signals coming from the analog section, a dsp unit computes the amount of consumed active energy. the active energy is available as a pulse frequency output and directly driven by a stepper counter. in the stpm1x an output signal with pulse frequency proportional to energy is generated. this signal is used in the calibration phase of the energy meter application allowing a very easy approach. when the device is fully configured and calibrated, a dedicated bit of otp block can be written permanently in order to prevent accidental entry into test mode or changing any configuration bit. tssop20 table 1. device summary order codes package packaging stpm11atr tssop20 (tape and reel) 2500 parts per reel stpm12atr tssop20 (tape and reel) 2500 parts per reel stpm13atr tssop20 (tape and reel) 2500 parts per reel STPM14ATR tssop20 (tape and reel) 2500 parts per reel www.st.com
contents stpm11/12/13/14 2/45 contents 1 schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1 measurement error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.2 adc offset error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.3 gain error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.4 power supply dc and ac rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.5 conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6 typical performance characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7 theory of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.1 general operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.2 analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.3 a/d converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.4 period and line voltage measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.5 single wire meter mode (stpm13/14 with rogowsky coil sensor) . . . . . 18 7.6 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.7 load monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.8 error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.9 tamper detection module (stpm13/14 only) . . . . . . . . . . . . . . . . . . . . . . 21 7.10 phase compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.11 clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.12 resetting the stpm1x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.13 energy to frequency conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.14 driving a stepper motor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.15 configuring the stpm1x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
stpm11/12/13/14 contents 3/45 7.16 mode signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.17 cfgi: configuration interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8 energy calculation algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9 stpm1x calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 10 schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 11 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 12 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
list of figures stpm11/12/13/14 4/45 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. pin connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. supply current vs supply voltage, t a = 25c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 4. rc oscillator frequency vs v cc , r =12 k , t a = 25c. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 5. rc oscillator: frequency jitter vs temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 6. analog voltage regulator: line - load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 7. digital voltage regulator: line - load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 8. voltage channel linearity at different v cc voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 9. power supply ac rejection vs v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 10. power supply dc rejection vs v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 11. error over dynamic range gain dependence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 12. primary current channel linearity at different v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 13. gain response of ad converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 14. clock frequency vs external resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 15. first order a/d converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 16. bandgap temperature variation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 17. tamper conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 18. different oscilla tor circuits (a); (b); (c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 19. positive energy or absolute computation en ergy (abs=1) step per driving signals . . . . . . 26 figure 20. negative energy stepper driving signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 21. timing for writing configuration and mode bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 22. active energy computation diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 23. charge pump schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 24. application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
stpm11/12/13/14 list of tables 5/45 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 1. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 2. absolute maximum ratings (see note) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 3. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 4. electrical characteristics (v cc = 5 v, t a = 25c, 2.2 f between v dda and v ss , 2.2 f between v ddd and v ss , 2.2 f between v cc and v ss unless otherwise specified) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 5. typical external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 9. rms voltage check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 10. nominal voltage values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 11. no load detection thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 12. different settings for led signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 13. configuration of mop and mon pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 table 14. configuration bits map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 15. mode signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 16. calibration entries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 17. device calculation constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 18. calibration results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 19. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
schematic diagram stpm11/12/13/14 6/45 1 schematic diagram figure 1. block diagram
stpm11/12/13/14 pin configuration 7/45 2 pin configuration figure 2. pin connections (top view) table 1. pin description pin n symbol type (1) name and function 1 mon p o output for stepper?s node 2 mop p o output for stepper?s node 3 scs d in enable or disable configuration interface for device configuration. 4v ddd a out 1.5 v output of internal low drop regulator which supplies the digital core. 5v ss gnd ground. 6v cc p in supply voltage. 7v otp p inr supply voltage for otp cells. 8v dda a out 3 v output of internal low drop regulator which supplies the analog part. 9i ip1 a in positive input of primary current channel 10 i in1 a in negative input of primary current channel 11 i ip2 a in positive input of secondary current channel (stpm13/14 only) 12 i in2 a in negative input of secondary current channel (stpm13/14 only) 13 v ip a in positive input of voltage channel 14 v in a in negative input of voltage channel 15 syn-np d i/o negative power indicator. (configuration interface) 16 clkin a in crystal oscillator input or resi stor connection if rc oscillator is selected 17 clkout a out oscillator output (rc or crystal) 18 scl/nlc d i/o no-load condition indicator. (configuration interface) 19 sdatd d i/o tamper detection indicator. (configuration interface) 20 led d o pulsed output proportional to active energy 1. a: analog, d: digital, p: power
maximum ratings stpm11/12/13/14 8/45 3 maximum ratings note: absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these condition is not implied table 2. absolute maximum ratings (see note) symbol parameter value unit v cc dc input voltage -0.3 to 6 v i pin current on any pin (sink/source) 150 ma v id input voltage at digital pins (scs, mop, mon, syn, sdatd, sclnlc, led) -0.3 to v cc +0.3 v v ia input voltage at analog pins (i ip1 , i in1 , i ip2 , i in2 , v ip , v in ) -0.7 to 0.7 v v otp input voltage at otp pin -0.3 to 25 v esd human body model (all pins) 3.5 kv t op operating ambient temperature -40 to 85 c t j junction temperature -40 to 150 c t stg storage temperature range -55 to 150 c table 3. thermal data symbol parameter value unit r thja thermal resistance junction-ambient 114.5 (1) c/w 1. this value is referred to single-layer pcb, jedec standard test board.
stpm11/12/13/14 electrical characteristics 9/45 4 electrical characteristics table 4. electrical characteristics (v cc = 5 v, t a = 25c, 2.2 f between v dda and v ss , 2.2 f between v ddd and v ss , 2.2 f between v cc and v ss unless otherwise specified) symbol parameter test conditions min. typ. max. unit energy measurement accuracy f bw effective bandwidth limited by digital filtering 5 400 hz error measurement error over the dynamic range (5% to 1000% of the calibration power value) 0.1 % snr signal to noise ratio over the entire bandwidth 52 db psrr dc power supply dc rejection voltage signal: 200mv rms /50hz current signal: 10mv rms /50 hz f clk = 4.194 mhz v cc =3.3v10%, 5 v10% 0.2 % psrr ac power supply ac rejection voltage signal: 200 mv rms /50 hz current signal: 10 mv rms /50 hz f clk = 4.194 mhz, v cc =3.3 v+0.2 v rms 1@100 hz v cc =5.0 v+0.2 v rms 1@100 hz 0.1 % general section v cc operating supply voltage 3.0 5.5 v i cc supply current configuration registers cleared or device locked (tstd=1) 4 mhz, v cc = 5 v 3.5 4 ma 8 mhz, v cc = 5 v 4.7 6 i cc increase of supply current per configuration bit, during programming 4 mhz, v cc = 5 v 120 a/bit increase of supply current per configuration bit with device locked 4 mhz, v cc = 5 v 2 por power on reset on v cc 2.5 v v dda analog supply voltage 2.85 3.0 3.15 v v ddd digital supply voltage 1.425 1.50 1.575 v f clk oscillator clock frequency mdiv bit = 0 4.000 4.194 mhz mdiv bit = 1 8.000 8.192 mhz f line nominal line frequency 45 65 hz v otp otp programming voltage 14 20 v i otp otp programming current per bit 2.5 ma t otp otp programming time per bit 100 300 s
electrical characteristics stpm11/12/13/14 10/45 i latch current injection latch-up immunity 300 ma analog inputs (i ip1 , i in1 , i ip2 , i in2 , v ip , v in ) v max maximum input signal levels voltage channel -0.3 0.3 v current channels gain 8x -0.15 0.15 v gain 16x -0.075 0.075 gain 24x -0.05 0.05 gain 32x -0.035 0.035 f adc a/d converter bandwidth 10 khz f spl a/d sampling frequency f clk /4 hz v off amplifier offset 20 mv z ip v ip , v in impedance over the total operating voltage range 100 400 k z in v ip1 , v in1 , v ip2 , v in2 impedance over the total operating voltage range 100 k g err current channels gain error 10 % i ilv voltage channel leakage current -1 1 a i leak current channel leakage current input disabled -1 1 a input enabled -10 10 digital i/o characteristics (sda-td, clkin, clkout, scs, syn-np, led) v ih input high voltage sda-td, scs, syn-np, led 0.75v c c v clkin 1.5 v il input low voltage sda-td, scs, syn-np, led 0.25v cc v clkin 0.8 v oh output high voltage i o = -2 ma v cc -0.4 v v ol output low voltage i o = +2 ma 0.4 v i up pull up current 15 a t tr transition time c load = 50 pf 10 ns power i/o characteristics (mop, mon) v oh output high voltage i o = -14 ma v cc -0.5 v v ol output low voltage i o = +14 ma 0.5 v t tr transition time c load = 50 pf 5 10 ns crystal oscillator (stpm12/14) table 4. electrical characteristics (v cc = 5 v, t a = 25c, 2.2 f between v dda and v ss , 2.2 f between v ddd and v ss , 2.2 f between v cc and v ss unless otherwise specified) symbol parameter test conditions min. typ. max. unit
stpm11/12/13/14 electrical characteristics 11/45 i i input current on clkin 1 a r p external resistor 1 4 m c p external capacitors 22 pf f clk nominal output frequency 4 4.194 mhz 8 8.192 rc oscillator (stpm11/13) i clkin settling current f clk = 4 mhz 40 60 a r set settling resistor 12 k t jit frequency jitter 1 ns on chip reference voltage v ref reference voltage 1.23 v reference accuracy 1 % t c temperature coefficient afte r calibration 30 50 ppm/c configuration interface timing f sclkw data write speed 100 khz t ds data setup time 20 ns t dh data hold time 0 ns t syn syn-np active width 2/f clk s table 4. electrical characteristics (v cc = 5 v, t a = 25c, 2.2 f between v dda and v ss , 2.2 f between v ddd and v ss , 2.2 f between v cc and v ss unless otherwise specified) symbol parameter test conditions min. typ. max. unit table 5. typical external components function component parameter value tolerance unit line voltage interface resistor divider r to r ratio v rms = 230 v 1650 1% v/v r to r ratio v rms = 110 v 830 1% line current interface current shunt current to voltage conversion ratio 0.2 5% mv/a current transformer 30 12% rogowsky coil 3 12%
terminology stpm11/12/13/14 12/45 5 terminology 5.1 measurement error the error associated with the energy measured by stpm1x is defined as: percentage error = [stpm1x (reading) - true energy] / true energy 5.2 adc offset error this is the error due to the dc component associated with the analog inputs of the a/d converters. due to the internal automatic dc offset cancellation, the stpm1x measurement is not affected by dc components in voltage and current channel. the dc offset cancellation is implemented in the dsp. 5.3 gain error the gain error is gain due to the signal channel gain amplifiers. this is the difference between the measured adc code and the ideal output code. the difference is expressed as a percentage of the ideal code. 5.4 power supply dc and ac rejection this parameter quantifies the stpm1x measurement error as a percentage of the reading when the power supplies are varied. for the psrr ac measurement, a reading at two nominal supply voltages (3.3 and 5 v) is taken. a second reading is obtained with the same input signal levels when an ac (200 mv rms /100 hz) signal is introduced onto the supply voltages. any error introduced by this ac sig nal is expressed as a percentage of reading. for the psrr dc measurement, a reading at two nominal supply voltages (3.3 and 5 v) is taken. a second reading is obtained with the same input signal levels when the supplies are varied 10%. any error introduced is again expressed as a percentage of the reading. 5.5 conventions the lowest analog and digital power supply voltage is named v ss which represents the system ground (gnd). all voltage specifications for digital input/output pins are referred to gnd. positive currents flow into a pin. sinking current means that the current is flowing into the pin and is positive. sourcing current means that the current is flowing out of the pin and is negative. the timing specifications of the signal treated by digital control are relative to clk out . this signal is provided by from the crystal oscilla tor of 4.194mhz nominal frequency or by the internal rc oscillator. an external source of 4.194mhz or 8.192mhz can be used. the timing specifications of signals of the cfgi interface are relative to the scl-nlc, there is no direct relationship between the clock (scl -nlc) of the cfgi interface and the clock of the dsp block. a positive logic convention is used in all equations.
stpm11/12/13/14 typical performance characteristics 13/45 6 typical performance characteristics figure 3. supply current vs supply voltage, t a =25c figure 4. rc oscillator frequency vs v cc , r=12 k , t a =25c figure 5. rc oscillator: frequency jitter vs temperature figure 6. analog voltage regulator: line - load regulation figure 7. digital voltage regulator: line - load regulation figure 8. voltage channel linearity at different v cc voltages
typical performance characteristics stpm11/12/13/14 14/45 figure 9. power supply ac rejection vs v cc figure 10. power supply dc rejection vs v cc figure 11. error over dynamic range gain dependence figure 12. primary current channel linearity at different v cc figure 13. gain response of ? ad converters figure 14. clock frequency vs external resistor 2 3 4 5 6 7 8 5101520 r [k ? ] f [mhz] crc=0 crc=1 crc=2
stpm11/12/13/14 theory of operation 15/45 7 theory of operation 7.1 general operation the stpm1x is able to perform active energy measurement (wide band or fundamental) in single-phase energy meter systems. due to the proprietary energy computation algorithm, stpm1x active energy is not affected by any ripple at twice the line frequency. the calibration is very easy and fast allowing calibration in only one point over the whole current range which allows saving time during the calibration phase of the meter. the calibration parameters are permanently stored in the otp (one time programmable) cells, preventing calibration tampering. several functions are programmable using internal configuration bits accessible through the configuration interface. the most important configuration bits are two configuration bits called pst that allow the selection of the sensor and the gain of the input amplifiers. the stpm1x is able to directly drive a stepper motor with the mop and mon pins, and provides information on tamper, no-load and negative power. two kinds of active energy can be selected to be brought to the led pin: the total active energy that includes all harmonic content up to 50 th harmonic and the active energy limited to the 1 st harmonic. this last energy value is obtained by filtering the wide band active energy. 7.2 analog inputs input amplifiers the stpm1x has one fully differential voltage input channel and one (stpm11/12) or two (stpm13/14) fully differential current input channels. the voltage channel consists of a differential amplifier with a gain of 4. the maximum differential input voltage for the voltage channel is 0.3 v. in stpm13/14, the two current channels are multiplexed (see tamper section for details) to provide a single input to a preamplifier with a gain of 4. the output of this preamplifier is connected to the input of a programmable gain amplifier (pga) with possible gain selections of 2, 4, 6, 8. the total gai n of the current channels will be then 8, 16, 24 , 32. the gain selections are made by writing to the gain configuration bits pst and it can be different for the two current channels. the maximum differential input voltage is dependent on the selected gain according to the ta bl e 6 : table 6. voltage channel voltage channels current channels gain max input voltage (v) gain max input voltage (v) 4 0.30 8x 0.15 16x 0.075 24x 0.05 32x 0.035
theory of operation stpm11/12/13/14 16/45 the table 7 and table 8 : below show the gain values according to the configuration bits: both the voltage and current channels implement an active offset correction architecture which has the benefit of avoiding any offset compensation. the analog voltage and current signals are processed by the analog to digital converters that feed the hardwired dsp. the dsp implements an automatic digital offset cancellation that makes possible avoiding any manual offset calibration on the analog inputs. 7.3 a/d converters the analog to digital conversion in the st pm1x is carried out using two first order converters. the device performs a/d conversi ons of analog signals on two independent channels in parallel. in stpm13/14, the current channel is multiplexed as primary or secondary current channel in order to be able to perform a tamper function. the converted signals are supplied to the internal hardwired dsp unit, which filters and integrates those signals in order to boost the resolution and to yield all the necessary signals for computations. a modulator converts the input signal into a continuous serial stream of 1s and 0s at a rate determined by the sampling clock. in the stpm1x, the sampling clock is equal to table 7. configuration of current sensors stpm11/12 current channel configuration bits gain sensor pst (2bi ts) addg (1 bit) 8 rogowsky coil 00 16 0 1 24 1 0 32 1 1 8ct2x 32 shunt 3 x table 8. configuration of current sensors stpm13/14 primary secondary configuration bits gain sensor gain sensor pst (2bits) addg (1 bit) 8 rogowsky coil 8 rogowsky coil 00 16 16 0 1 24 24 1 0 32 32 1 1 8 ct 8ct2 x 8 32 shunt 3 x
stpm11/12/13/14 theory of operation 17/45 f clk /4. the 1-bit dac in the feedback loop is driven by the serial data stream. the dac output is subtracted from the input signal. if the loop gain is high enough, the average value of the dac output (and therefore the bit stream) can approach that of the input signal level. when a large number of samples are averaged, a very precise value of the analog signal is obtained. this averaging is carried out in the dsp section which implements decimation, integration and dc offset cancellation of the supplied signals. the gain of the decimation filters is 1.004 for the voltage channel and 0.502 for the current channel. the resulting signal has a resolution of 11bits for voltage channel and 16 bits for current channel. 7.4 period and line voltage measurement the period module measures the period of base frequency of voltage channel and checks if the voltage signal frequency is in the band from f clk /2 17 to f clk /2 15 . an internal signal is produced at every positive peak of the line voltage. if the counted number of pulses between two trailing edges of this signal is higher than the f clk /2 17 hz equivalent pulses or if the counting is stopped (internal signal is not available), it means that the base frequency is lower than f clk /2 17 hz and an internal error flag bfr (base frequency range) is set. if the counted number of pulses within one line period is higher than the f clk /2 15 equivalent pulses, the base frequency exceeds the limit. in this case, such error must be repeated three times in a row, in order to set the error flag bfr. the bfr flag is also set if the value of th e rms voltage drops below a certain value (bfr- on) and it is cleared when the rms voltage goes above bfr-off threshold. the table below shows the equivalent rms voltage on the v ip /v in pins according to the value of the voltage channel calibrator. the bfr flag is also set if the rms voltage across v ip -v in drops below a threshold value calculated with the following formula: (ct/shunt) figure 15. first order a/d converter dac - + integrator f clk /4 input analog signal output digital signal v bfr irms k v ? = ? 6703 64
theory of operation stpm11/12/13/14 18/45 (rogowsky) where k v is the voltage calibrator value ranging from 0.875 to 1.000. the bfr flag is cleared when the v irms value goes above twice v irms-bfr . when the bfr error is set, the computation of power is suspended and mop, mon and led will be held low. 7.5 single wire meter mode (stpm13/14 with rogowsky coil sensor) stpm1x supports the single wire meter (s wm) operation when working with rogowsky coil current sensors. in swm mode there is no available voltage information in the voltage channel. it is possible that someone has disconnected one wire (live or neutral) of the meter for tampering purposes or in case the line voltage is very stable, it is possible to use a predefined value for computing the energy without sensing it. in order to enable the swm mode, the stpm1x must be configured with pst values of 0 or 1. in this way, if the bfr error is detected, stpm1x enters in swm. if bfr is cleared, the energy calculation is performed normally. when bfr is set (no voltage information is available), the energy computation is carried out using a nominal voltage value according to the nom configuration bits. since there is no information on the phase shift between voltage and current, the apparent rather than active power is used for tamper and energy computation. the calculated apparent energy will be the product between i rms (effectively measured) and an equivalent v rms that can be calculated as follows: v rms =vpk*k nom , where vpk represents the maximum line voltage reading of the stpm1x and k nom is a coefficient that changes according to ta b l e 1 0 : v bfr irms k v ? = ? 6687 64 table 9. rms voltage check bfr-on bfr-off rogowsky 0.009571/kv 0.019142/kv ct-shunt 0.0078/kv 0.0156/kv table 10. nominal voltage values nom k nom 00.3594 10.3906 20.4219 30.4531
stpm11/12/13/14 theory of operation 19/45 for example, if r1 = 783k and r2 = 475 are used as resistor divider when the line voltage is present, the positive voltage present at the input of the voltage channel of stpm1x is: since the maximum voltage value applicable to the voltage channel input of stpm1x is +0.3v, the equivalent maximu m line voltage applicable is: v pk = r 1 +r 2 /r 2 ? 0.3 = 494.82 considering the case of nom=2, the correspondent rms values used for energy computation is: v rms = v pk ? 0.4219 = 208.76 [v] usually the supply voltage for the electronic me ter is taken from the line voltage. in swm, since the line voltage is no longer present, another power source must be used in order to provide the necessary supply to stpm1x and the other electronic components of the meter. 7.6 power supply the main stpm1x supply pin is the v cc pin. from the v cc pin two linear regulators provide the necessary voltage for the analog part v dda (3 v) and for the digital part v ddd (1.5 v). the v ss pin represents the reference point for all the internal signals. the 100nf capacitor should be connected between v cc and v ss , v dda and v ss , v ddd and v ss . all these capacitors must be located very close to the device. the stpm1x contains a power-on-reset (por) detection circuit. if the v cc supply is less than 2.5 v, then the stpm1x goes into an inactive state, all the functions are blocked asserting and a reset condition is set. this is useful to ensure that the correct device operation at power-up and during power-down. the power supply monitor has built-in hysteresis and filtering, which give a high degree of immunity to false triggering due to noisy supply voltages. a bandgap voltage reference (vbg) of 1.23 v 1% is used as reference voltage level source for the two linear regulators and for the a/d converters. also, this module produces several bias currents and voltages for all other analog modules and for the otp module. the bandgap voltage temperature behavior can be changed in order to better compensate the variation of sensor sensitivity with temperature. this task is performed with the bgtc configuration bits. 2 2 1 2 rms v r r r vi ? + =
theory of operation stpm11/12/13/14 20/45 7.7 load monitoring the stpm1x include a no-load condition detection circuit with adjustable threshold. this circuit monitors the voltage and the current channels and, when the measured power is below the set threshold, the internal signal bil becomes high. the information about this signal is also available in the status bit bil. the no load condition occurs when the product between vrms and irms input values is below a given value. this value can be set wit h the ltch configuration bits, and it is also dependent on the selected current gain (ai) and the calibration registers constant kp=kv*ki. four different no-load threshold values can be chosen according to the two configurations bits ltch (see ta b l e 1 1 ). when a no-load condition occurs (bil=1), the integration of power is suspended and the tamper module is disabled. if a no-load condition is detected, the bil signal blocks generation of pulses for stepper and forces the sclnlc pin to be low. figure 16. bandgap temperature variation table 11. no load detection thresholds ltch vrms * irms (input channel voltages ) vrms * irms (input channel voltages) rogowski coil (pst<2 ) ct or shunt (pst>1) 0 0.004488 / (ai*kp) 0.003648 / (ai*kp) 1 0.008976 / (ai*kp) 0.007296 / (ai*kp) 2 0.017952 / (ai*kp) 0.014592 / (ai*kp) 3 0.035904 / (ai*kp) 0.029184 / (ai*kp)
stpm11/12/13/14 theory of operation 21/45 7.8 error detection in addition to the no-load condition and the line frequency band, the integration of power can be suspended also due to detected error on the source signals. there are two kinds of error detection circuits involved. the first checks all the signals from the analog part if any are stacked at 1 or 0 within the 1/128 of f clk period of observation. in case of detected error the corresponding signal is replaced with an idle signal, which represents a constant value 0. another error, condition occurs if the mop, mon and led pin outputs signals are different from the internal signals that drive them. this ca n occur if some of this pin is forced to gnd or to some other imposed voltage value. 7.9 tamper detection module (stpm13/14 only) the stpm13/14 is able to measure the current in both live and neutral wires. this mechanism has been adapted to implement an anti-tamper function. if this function is selected (see table 8 :), the live and neutral wire currents are monitored. when a difference between the two measurements is detected, the stpm13/14 enters the tamper state. when there is a very small difference between the two channels, the stpm13/14 is in normal state. in particular, both channels are not constant ly observed. a time mu ltiplex mechanism is used. during the observation time of the selected channel, its active energy is calculated. the detection of a tamper condition occurs when the absolute value of the difference between the two active energy values is greater than a certain percentage of the averaged energy during the activated tamper module. this percentage value can be selected between two different values (12.5% and 6.25%) according to the value of the configuration bit crit. the tamper condition will be detected when the followin g formula is satisfied: energych1 - energych2 > k crit (energych1 + energych2)/2; where k crit can be 12.5% or 6.25%. the detection threshold is much higher than the accuracy difference of the current channels, which should be less than 0.1%. some margin should be left for a possible transition effect, due to accidental synchronism between the actual load current change and the rhythm of taking the energy samples. the tamper circuit works if the energies asso ciated with the two cu rrent channels will be both positive or both negative. if the two energies have different signs, the tamper remains on constantly. however, the channel with the associated higher power is selected for the final computation of energy. in single wire mode, the apparent energy rather than active is used for tamper detection. detailed operational description normal state the meter is initially set to normal state, i.e. tamper not detected. in such state, we expect that the values of both load currents should not differ more than the accuracy difference of the channels. for this reason, we can use an av erage value of currents of both channels for the active energy calculation. the average is implemented with the multiplex ratio of 32:32 periods of line per channel. this means that for 32 periods of line voltage, i.e. 640ms at 50 hz, the current of the primary channel is used for the calculation followed by another 32
theory of operation stpm11/12/13/14 22/45 periods of line voltage when the current of secondary channel is used instead. four periods before the primary to secondary switching point, a tamper detection module is activated. it is deactivated after eight periods of line have elapsed. this means that energy of four periods of primary channel immediately followed by ener gy of four periods of secondary channel is sampled within the tamper module. we shall call those samples a and b respectively. from these two samples the criteria of tamper detec tion is calculated. if four consecutive new results of criteria happen, i.e. after elapsed 5.12s at 50 hz, the meter will enter into tamper state tamper state within this state the multiplex ratio will change either to 60:4, when primary current is higher than secondary, or to 4:60 otherwise. thus, the channel with the higher current is used in the energy calculation. the energy is not aver aged by the mentioned ratio, rather the last measured higher current is used also during 4 line period gap. the gap is still needed in order to monitor the samples of the non-selected channel, which should check when the tamper detected state is changed to either normal or another tamper detected state. several cases of transition of the state are shown in the figure 17 - below the detected tamper condition is stored in the bit signal. this signal is connected to the sda-td pin. when this pin is low, a tamper condition has been detected. figure 17. tamper conditions
stpm11/12/13/14 theory of operation 23/45 when internal signals are not good enough to perform the computation, i.e. line period is out or range or signals from the analog part are stacked at high or low logic level, or no load condition is activated, the tamper module is disabled and its state is preset to normal. 7.10 phase compensation the stpm1x is does not introduce any phase shift between voltage and current channels. however, the voltage and current signals come from transducers, which could have inherent phase errors. for example, a phase error of 0.1 to 0.3 is not uncommon for a current transformer (ct). these phase errors can vary from part to part, and they must be corrected in order to perform accurate power calculations. the errors associated with phase mismatch are particularly noticeable at low power factors. the stpm1x provide a means of digitally calibrating these small phase errors through a introducing delays on the voltage or current signal. the amount of phase compensation ca n be set using the 4 bits of the phase calibration register (cph). the default value of this register is at a value of 0 which gives 0 phase compensation. a cph value of 15 (1111) introduces a phase compensation of +0.576. this compensates the phase shift usually introduced by the current sensor, while the voltage sensor, normally a resistor divider, does not introduce any delay. the resolution step of the phase compensation is 0.038. 7.11 clock generator all the internal timing of the stpm1x is based on the clk out signal. this signal is generated by different circuits according to the stpm1x version. stpm11/13: internal rc oscillator. a resistor connected between clk in and ground will set the rc current. for 4 mhz operation the suggested settling resistor is 12 k ; the oscillator frequency can be compensat ed using the crc configuration bit (see ta bl e 1 3 and figure 14 ) stpm12/14: quartz oscillator. the oscillator circuit is desi gned to support an external crystal. the suggested circuit is depicted in figure 18 . these versions support also an external oscillator signal source th at must be conne cted to the clk out pin. the clock generator is powered from analog su pply and is responsible for two tasks. the first one is to retard the turn-on of some function blocks after por in order to help smooth start of external power supply circuitry by keeping all major loads off. the second task of the clock generator is to provide all necessary clocks for analog and digital parts. within this task, the mdiv configuration bit is used to inform the device about the nominal frequency value of clk out . the suggested operation frequency range is from 4.000 mhz to 4.194 mhz.
theory of operation stpm11/12/13/14 24/45 7.12 resetting the stpm1x the stpm1x has no reset pin. the device is automatically reset by the por circuit when the v cc crosses the 2.5 v value. when the reset occurs, all clocks and both dc buffers in the analog part are kept off for about 30ms and all blocks of the digital part are held in a reset state for about 125 ms after a reset condition. resetting the stpm1x causes all the functional modules of stpm1x to be cleared including the otp shadow latches (see 7.15 for otp shadow latches description) 7.13 energy to frequency conversion the stpm1x provides energy to frequency conversion both for calibration and energy readout purposes. in fact, one convenient way to verify the meter calibration is to provide a pulse train signal with 50% duty cycle whose fre quency signal is proportional to the active energy under steady load conditions. it is convenient to have high frequency pulses during calibration phase and low frequency for readout purposes; stpm1x supports both cases. let's suppose to choose a certain number of pulses on the led pin (h igh frequency) that will corresponds to 1 kwh. we will name this value as p. the active energy frequency-based signal is available in the led pin. the led is driven from internal signal aw (active energy) whos e frequency is proportional to the active energy. the desired p is achieved acting on the digital calibrators during the calibration procedure. the apl configuration bit changes the internal divider that provides the signal on the led pin according to ta b l e 1 2 , setting apl=1 the number of pulses are reduced in order to provide low frequency pulses for readout purposes. the division factor is set according to kmot configuration bits. in this case the pulses will have a fixed width of 31.25 ms. figure 18. different oscillator circuits (a); (b); (c) stpm12/14 with external source stpm12/14 with quartz stpm11/13
stpm11/12/13/14 theory of operation 25/45 due to the innovative and proprietary power calculation algorithm, the frequency signal is not affected by any ripple at twice the line frequency. this feature strongly reduces the calibration time of the meter. 7.14 driving a stepper motor the stpm1x is able to directly drive a stepper motor. an internal divider (mono-flop and decoder) generates stepper driving signals ma and mb from signal aw. the ma and mb signals are brought to the mop and mon pins that are able to drive the stepper motor. several kinds of selections are possible for the driving signals according to the configuration bits lvs and kmot. the numbers of pulses per kwh (pm) in the mop and mon outputs are linked with the number of pulses of the led p (see previous paragraph - 7.13) pin with the following relationship. the mono-flop limits the length of the pulses according to the lvs bit value. the decoder distributes the pulses to ma and mb alternatively, which means that each of them has only one half of selected frequency. in case of detected negative power the behavior of mop and mon depends on the abs configuration bit status. if this bit is set, the negative power is computed as it was positive (absolute value), and the mop and mon signals maintain the pulse sequence in order to keep the forward rotation direct ion of the motor. if abs is zero, negative power is computed with its own sign, and the mop and mon signals invert their logic state in order to make the backward rotation direction of the motor. see the diagram below. table 12. different settings for led signal kmot (2 bits) apl=0 apl=1 pulses pulses 0 p p/64 1 p/128 2 p/32 3 p/256 table 13. configuration of mop and mon pins lvs (1 bit) kmot (2 bits) pulses length pm 0 0 31.25 ms p/64 0 1 31.25 ms p/128 0 2 31.25 ms p/32 0 3 31.25 ms p/256 1 0 156.25 ms p/640 1 1 156.25 ms p/1280 1 2 156.25 ms p/320 1 3 156.25 ms p/2560
theory of operation stpm11/12/13/14 26/45 when a no-load condition is detected mop and mon are held low. 7.15 configuring the stpm1x all the configuration bits that control the operation of the device can be written temporarily or permanently. for temporary writing, the configuration bits value are written in the shadow registers which are simple latches that hold the configuration data. for permanent writing, the configuration bits are stored in the otp (one time programmable) cells that keep the information for an undefined period of time even if the stpm1x is without supply, but, once written, they cannot be changed. the temporary writing is useful mainly during testing of the device or during the calibration phase. all the configuration parameters can be changed an infinite number of times in order to test the device operation. the shadow registers are cleared whenever a reset condition occurs. the configuration bits are different for stpm11/12 and for stpm13/14 due to the presence of the tamper module. each of them consis ts of paired elements, one is latch (the otp shadow), and one is the otp anti-fuse element. when the stpm1x is released in the market, all anti-fuses represent logic low state but they can be written by the user in order to configure the stpm1x. this means that stpm1x can retain these bits of information even if it has been unsupplied for an undefined time. that's why the cfg signals are used to keep certain configuration and calibration values of the device. figure 19. positive energy or absolute computation energy (abs=1) stepper driving signals hi lo hi lo mon mop figure 20. negative energy stepper driving signals hi lo hi lo mon mop
stpm11/12/13/14 theory of operation 27/45 the very first cfg bit, called tstd, is used to disable any change of system signals after it has been permanently set. during the configuration phase, each bit set to logic level 1 increases the supply current of stpm01 of about 120 a, until the tstd bit is set to 1. the residual increase of supply current is 2 a per each bit set to 1. it is then recommended to set the tstd bit to 1 after the configuration procedure in order to keep the supply current as low as possible. the stpm1x can work either using the data stored in the otp cells or the data available in the shadow latches. this can be chosen according to the value rd mode signal (see paragraph 7.16 for description). if the rd is set, the cfg bits originates from corresponding otp shadow latches. if the rd is cleared, the cfg bits originates from corresponding otp anti-fuses. in this way, it is possible to temporarily set up certain configurations or calibrations of the device then verify and change, if necessary. this exercise is extensively used during production tests. each configuration bit can be written sending a byte command to stpm1x through its configuration interface. the procedure to write the configuration bits is described in the configuration interface section ( 7.17 ). after the tstd bit has been set, no other command can be sent to the stpm1x. this implies that the shadow latches can no longer be used as source of configuration data. table 14. configuration bits map address name n. of bits description (1) 6-bit binary dec 000000 0 tstd 1 test mode and otp write disable: - tstd=0: testing and continuous pre-charge of otp when in read mode, - tstd=1:normal operation and no more writes to otp 000001 1 mdiv 1 measurement frequency range selection: - mdiv=0: 4.000mhz to 4.194mhz, - mdiv=1: 8.000mhz to 8.192mhz 000011 3 apl 1 led pin frequency output: - apl=0: p - apl=1: kmot=0 p/64 kmot=1 p/128 kmot=2 p/32 kmot=3 p/256 000101 5 pst 2 current channel sensor type, gain and tamper selection: stpm11/12 - pst=0: primary is rogowsky coil x8 (x16 if addg=1) - pst=1: primary is rogowsky coil x24 (x32 if addg=1), - pst=2: primary is ct x8, - pst=3: primary is shunt x32, stpm13/14 - pst=0: primary is rogowsky coil x8 (x16 if addg=1), secondary is rogowsky coil x8 (x16 if addg=1), - pst=1: primary is rogowsky coil x24 (x32 if addg=1), secondary is rogowsky coil x24 (x32 if addg=1), - pst=2: primary is ct x8, secondary is ct x8 - pst=3: primary is ct x8, secondary is shunt x32 000110 6 (1)
theory of operation stpm11/12/13/14 28/45 001010 10 fund 1 this bit swaps the energy type between fundamental or wide band. - fund=0: wide band active energy up to 50 th harmonic; - fund=1: fundamental active energy 001011 11 abs 1 power accumulation type selection: - abs=0: signed accumulation, - abs=1: absolute accumulation 001100 12 lt c h 2 no-load condition constant: ltch=0 800 ltch=1 1600 ltch=2 3200 ltch=3 6400 001101 13 (1) 001110 14 kmot 2 constant of stepper pulses/kwh (see par. 7.14) selection: if lvs=0, kmot=0 p/64 kmot=1 p/128 kmot=2 p/32 kmot=3 p/256 if lvs=1, kmot=0 p/640 kmot=1 p/1280 kmot=2 p/320 kmot=3 p/2560 001111 15 (1) 010010 18 bgtc 2 bandgap temperature compensation bits. see figure 16. for details. 010011 19 (1) 010100 20 cph 4 4-bit unsigned data for compensation of phase error, 0+0.576 16 values are possible with a comp ensation step of 0.0384. when cph=0 the compensation is 0, when cph=15 the compensation is 0.576. 010101 21 010110 22 010111 23 (1) 011000 24 chv 8 8-bit unsigned data for voltage channel calibration. 256 values are possible. when chv is 0 the calibrator is at -12.5% of the nominal value. when chv is 255 the calibrator is at +12.5%. the calibration step is then 0.098%. 011001 25 011010 26 011011 27 011100 28 011101 29 011110 30 011111 31 (1) table 14. configuration bits map (continued) address name n. of bits description (1) 6-bit binary dec
stpm11/12/13/14 theory of operation 29/45 7.16 mode signals the stpm1x includes four mode signals. these signals change some of the operation of the stpm1x. the mode signals are not retained when the stpm1x supply is not available and then they are cleared when a por occurs. 100000 32 chp 8 8-bit unsigned data for primary current channel calibration. 256 values are possible. when chp is 0 the calibrator is at -12.5% of the nominal value. when chp is 255 the calibrator is at +12.5%. the calibration step is then 0.098%. 100001 33 100010 34 100011 35 100100 36 100101 37 100110 38 100111 39 (1) 101000 40 chs 8 stpm13/14 only 8-bit unsigned data for secondary current channel calibration. 256 values are possible. when chs is 0 the calibrator is at -12.5% of the nominal value. when chs is 255 the calibrator is at +12.5%. the calibration step is then 0.098%. 101001 41 101010 42 101011 43 101100 44 101101 45 101110 46 101111 47 (1) 110000 48 crc 2 stpm11/13 only 2-bit unsigned data for calibration of rc oscillator. (see typical characteristics in) crc=0, or crc=3 cal=0% crc=1, cal=+10%; crc=2, cal=-10% 110001 49 (1) 110010 50 nom 2 2-bit modifier of nominal voltage for single wire meter. nom=0: k nom =0.3594 / nom=1: k nom =0.3906 / nom=2: k nom =0.4219 / nom=3: k nom =0.4531 110011 51 (1) 110100 52 addg 1 selection of additional gain on current channels: addg=0: gain+=0 / addg=1: gain+=8 110101 53 crit 1 stpm13/14 only selection of tamper threshold: crit =0: 12,5% / crit =1: 6,25% 110110 54 lvs 1 type of stepper selection: lvs=0: pulse width 31.25 ms, 5v, / lvs=1: pulse width, 156.25 ms, 3v 1. important: this bit represents the msb of the decimal value indicated in the description column. table 14. configuration bits map (continued) address name n. of bits description (1) 6-bit binary dec
theory of operation stpm11/12/13/14 30/45 the mode signals bit can be written using the normal writing procedure of the cfgi interface (see cfgi par. 7.17) ? rd mode signal has been already described in par. 7.15 (configuring the stpm1x), but there is another implied function of the signal rd. when it is set, each sense amplifier is disconnected from corresponding anti-fuse element and this way, its 3v nmos gate is protected from the high voltage of v otp during permanent write operation. this means that as long as the v otp voltage reads more than 3v, the signal rd should be set. ? pump. when set, the pump mode signal transforms the mop and mon pins to act as driving signals to implement a charge-pump dc-dc converter (see figure 23 ). this feature is useful in order to boost the v cc supply voltage of the stpm1x to generate the v otp voltage (14 v to 20 v) needed to program the otp anti-fuse elements. ? we (write enable): this mode signal is used to permanently write to the otp anti- fuse element. when this bit is not set, any writing to the configuration bit is recorded in the shadow latches. when this bit is set, the writing is recorded both in the shadow latch and in the otp anti-fuse element. 7.17 cfgi: configuration interface the cfgi interface supports a simple serial protocol, which is implemented in order to enable the configuration of stpm1x which allows writing the mode bits and the configuration bits (temporarily or permanently); four pins of the device are dedicated to this purpose: scs, syn-np, sclncn, sdatd. scs, syn-np, scl-nlc and sdatd are all input pins. a high level signal for these pins means a voltage level higher than 0.75xv cc , while a low level signal means a voltage value lower than 0.25xv cc . the condition in which scs, syn-np and scl-nl c inputs are set to high level determines the idle state of the cfgi interface and no data transfer occurs. ? scs : in the stpm1x, the syn-np, scl-nlc and sda-td have the dual task to provide information on the meter status (see pin description table) and to allow cfgi communication. the scs pin allows using the above pins for cfgi communication when it is low and allows the normal operation of syn-np, scl-nlc and sda-td table 15. mode signals description signal name bit value status binary command hex command pump 0 mop and mon operate normally 0111000x 70 or 71 1 mop and mon provide the driving signals to implement a charge-pump dc-dc converter 1111000x f0 or f1 rd 0 the 56 configuration bits originated by otp anti-fuses 0111101x 7a or 7b 1 the 56 configuration bits originated by shadow latches 1111101x fa or fb we 0 any writing in the configuration bits is recorded in the shadow latches 0111110x 7c or 7d 1 any writing in the configuration bits is recorded both in the shadow latches and in the otp anti-fuse elements 1111110x fc or fd
stpm11/12/13/14 theory of operation 31/45 when it is high. in this section, the syn-np, scl-nlc and sda-td operation as part of the cfgi interface is described. ? syn-np : this pin allows synchronization of the communication between stpm1x and the host. see figure 19 - for detailed timing of the pin. ? scl-nlc : it is basically the clock pin of the cfgi interface. this pin function is also controlled by the scs status. if scs is low, scl-nlc is the input of the serial bit synchronization clock signal. when scs is high, scl-nlc is also high which determines the idle state of the cfgi. ? sda-td is the data pin. sda-td is the input of the serial bit data signal. any pin above has internal weak pull up device of nominal 15 a. this means that when a pin is not forced by external signals, the state of the pin is logic high. a high state of any input pin above is considered as an idle (not active) state. for the cfgi to operate correctly, the stpm1x must be correctly supplied as described in the power supply section. when scs is active (low), signal sda-td should change it s state at trailing edge of signal scl-nlc and the signal sda-td should be stable at the next leading edge of signal scl-nlc. the first valid bit of sda-td always starts with the activation of signal scl-nlc. writing procedure each writable bit (configuration and mode bits) has its own 6-bit absolute address. for the configuration bits, the 6-bit address value corresponds to its decimal value, while for the mode bits, the addresses are the ones indicated in the mode signal paragraph (7.16). in order to change the latch state, a byte of data must be sent to stpm1x via cfgi. this byte consists of 1-bit data to be latched (msb), followed by 6-bit address of destination latch, followed by 1-bit don't care data (lsb) which totals 8 bits of command byte. for example, if we would like to set the configuration bit 52 (additional gain of 8) to 1, we must convert the decimal 52 to its 6-bit bi nary value: 110100. th e byte command will be then composed like this: 1 bit data value+6-bits address+1 bit (0 or 1) as depicted in figure 19 -. in this case the binary command will be 11101000 (0xe8) or 11101001 (0xe9). figure 21. timing for writing configuration and mode bits
theory of operation stpm11/12/13/14 32/45 t 1 t 2 (>30ns): cfgi out of idle state t 2 t 3 (>30ns): cfgi enabled for write operation t 3 : data value is placed in sda t4: sda value is stable and shifted into the device t 3 t 5 (>10s): writing clock period t 3 t 5 : 1 bit data value t 5 t 6 : 6 bits address of the destination latch t 6 t 7 : 1 bit exe command t 8 : end of cfgi writing t 9 : cfgi enters idle state the same procedure should be applied for the mode signals, but in this case the 6-bits address must be taken from the ta b l e 1 4 . the lsb of command is also called exe bit because instea d of data bit value, the corresponding serial clock pulse is used to generate the necessary latching signal. in this way the writing mechanism does not need the measurement clock in order to operate, which makes the operation of cfgi module of stpm1x completely independent from the rest of the device logic except from the signal por. commands for changing system signals should be sent during active signals scs and syn- np as it is shown in the figure 19 -. a string of commands can be send within one period of active signals scs and syn-np. permanent writing of the cfg bits in order to make a permanent set of some cfg bits, use the following procedure: 1. collect all addresses of cfg bits to be permanently set into a list; 2. clear all otp shadow latches; 3. set the system signal rd; 4. connect a current source of at least +14v, 1ma to 3ma to votp; 5. wait for votp voltage to be stable; 6. set one otp shadow latch from the list; 7. set the system signal we; 8. wait for 300 s; 9. clear the system signal we; 10. clear the otp shadow latch which was set in step 6; 11. until all cfg bits are permanently set as desired, repeat steps 5 to 11; 12. disconnect the current source; 13. wait for votp voltage to be less than 3v; 14. clear the system signal rd; 15. verify the correct writing, testing stpm1x operation; 16. if the verification of cfg bits fails, repeat steps 1 to 16. for steps of set or clear, apply the timing shown in figure 19 - with proper signal on the sda-td. in order to create a permanent set of the tstd bit, which does not result in any more writing to the configuration bits, the procedure above must be conducted in such a way that steps 6
stpm11/12/13/14 theory of operation 33/45 to 13 are performed in series during a single period of active scs. the idle state of scs would make the signal tstd immediately effective which in turn, would abort the procedure and possibly destroy the device due to clearing of system signal rd. this would result in the connecting of all gates of 3 v nmos sense amplifiers of already permanently set cfg bits to the v otp source.
energy calculation algorithm stpm11/12/13/14 34/45 8 energy calculation algorithm inside the stpm1x the computing section of the measured active power uses a completely new patented signal process approach. this ap proach allows the device to reach high performances in terms of accuracy. the signals, coming from the sensors, for the instantaneous voltage is: v(t) = v?sin t; where v is the peak voltage and is related to the line frequency (see[1]) and the instantaneous current is: i(t) = i ? sin ( t + ? ); where i is the peak current, is related to the line frequency and ? is the phase difference between voltage and current (see[2]) active power in the stpm1x, after the pre-conditioning and the a/d conversion, the digital voltage signal (which is dynamically more stable with respect to the current signal) is processed by a differentiate stage which transforms: v(t) v?(t) = dv/dt = v ? ? cos t ? [eq. 1 - see (5) in figure 6 ] the result, together with the pre-processed and digitalized current signal: figure 22. active energy computation diagram
stpm11/12/13/14 energy calculation algorithm 35/45 i(t) = i ? sin(t + ? ); [eq. 2 - see (6) in figure 6 ] can then be used to calculate. these digital si gnals are also used in two additional steps for integration, obtaining: dv/dt v(t) = v ? sin t ; [eq. 3 - see (7) in figure 6 ] [eq. 4 - see (8) in figure 6] now four signals are available. combining ( pairing) them by two multiplication steps two results are obtained: [eq. 5 - see (9) in figure 6 ] [eq. 6 - see (10) in figure 6 ] after these two operations, another stage another step involves the subtraction of p1 from p2 and dividing the result by 2, to obtain the active power: [eq. 7 - see (11) in figure 6 ] in this way, the ac part has been then removed from the instantaneous power. in the case of current sensors like "rogowski coils", which provide the rate of the instantaneous current signal, the initial voltage signal differentiation stage is switched off. in this case the signals coming from the a/d conv ersion and their consequent integrations are: v(t) = v ? sin (t ); [eq. 8] [eq. 9] [eq. 10] ) cos( ) ( ) ( ? + ? ? = ? = t i dt t i t i i(t) ? 2 ) 2 cos( 2 cos ) ( ) ( 1 ? ? + ? ? ? ? ? ? = ? ? = / t i v i v dt t i dt dv t p 2 ) 2 cos( 2 cos ) ( ) ( ) ( 2 ? ? + ? ? ? ? ? = ? = / t i v i v t i t v t p 2 cos 2 )) ( ) ( ( ) ( 1 2 ? ? ? = / ? / = i v t p t p t p ? ? ? ? ? ? + ? ? 2 ) 2 cos( ? t i v ) cos( ) ( ) ( ? + ? ? ? = = t i dt t di t i t v dt t v t v cos ) ( ) ( ? ? = ? =
energy calculation algorithm stpm11/12/13/14 36/45 [ [eq. 11] the signals process flow is the same as shown in the previous case, and even with the formulas above, the result is the same. the absence of any ac component allows a very fast calibration procedure. averaging the readings of several line periods is not needed. the active energy measurement is already stable after one line cycle. moreover the digita l calibration allows saving time and space compared to the hardware calibration made with resistor strings. ) sin( ) ( ) ( ) ( ? + ? ? = = ? = t i t i dt t i t i
stpm11/12/13/14 stpm1x calibration 37/45 9 stpm1x calibration energy meters based on stpm1x devices are calibrated on the frequency of the output pulse signal. the devices are comprised of two independent meter channels for line voltage and current respectively. each channel includes its own digital calibrator, to adjust the voltage and current signals coming from the sensors in the range of 12.5% in 256 steps. a digital filter is included to remove any signal dc component. the devices produce an energy output pulse sign al whose frequency is proportional to the measured active energy. the devices have an embedded memory, 54 bits, used for configuration and calibration purposes. the value of these bits can be written temporarily or permanently through cfgi communication channel. the basic information needed to start the calibration procedure is found in ta bl e 1 6 and ta bl e 1 7 : the following typical stpm01 parameters and constants are also known: av is constant. while, ai is chosen according to the sensor gv and gi are constant cv and ci are 8bits register (chv, chp and chs) from the values above and for both the given amplification factor and initial calibration data, the following target values can be calculated: considering that ci=0 generates a correction of 75% and that ci=128 determines a correction factor of 87.5%, and the same for cv, the total correction for the power stands within kp = kv*ki = (0.75*0.75)=56.25% and 100%, and cv=ci=128 gives a correction factor of kp= (0.875*0.875) = 76.5625% table 16. calibration entries symbol description value vn line rms voltage (230 v) in line rms current (5 a) p power sensitivity (led: p=128000 pulses/kwh, stepper motor: pm=p/64= 2000 pulses/kwh) si shunt sensor 0,42 mv/a table 17. device calculation constants symbol description value vbg reference voltage (1.23 v 2%) fm clock (2 23 hz 50ppm) av, ai amplification of adc (4 1%, (8, 16, 24, 32) 2%)) gp gain of voltage and current decimation filters (0.504008) cv, ci calibration data range (min = 0, ini = 128, max = 255) dl aw bit position that generates led signal (2 11 )
stpm1x calibration stpm11/12/13/14 38/45 each calibrator value can be changed from a binary form to a decimal correction form, using the following formula: kv=(cv/128)*0.125 + 0.75 and the same for ki. let us choose as initial value ai=32 from the target power constant c p of the meter and the actual values of v rms and i rms , which are applied to the meter under calibration, the error of power measurement can be calculated: err = 100(fx/f -1) [%], where fx is the real frequency read at led output. now, a final unit less power reduction factor can be calculated: p f = (p d - err)/100 this final power reduction factor can be considered as a product of voltage and current reduction factors which are produced from corresponding calibration constants. so, an obvious solution to obtain the voltage and current reduction factors is to calculate a common reduction factor as a square root of pf. this result must fall within the indicated range, otherwise the device cannot be calibrated: 768 r = 1024 pf + 0.125 < 1024 in order to obtain the corresponding calibration constants, the reduction factor must be transformed: cv = cc = r - 768 by using separately the integer and the fractional part of the common reduction a better fit of calibration constants can be produced. simply, let's set one of the two calibration registers (e.g. cv) to the lowest integer value of r, while the other (cc) should be set to the nearest integer value of r. examples: r-768=128.124; in this case set cv=128; set cc=128 r-768=127.755; while in this other one set cv=127; set cc=128. note: stpm13/14: each current channel must be calibrated separately. in order to do this, follow these steps: apply the nominal test voltage to the voltage sensor, and the nominal test current to the primary current channel sensor. do not apply such current on the secondary current channel sensor. adjust the voltage and primary current calibrators (see above). disconnect the nominal test current from the primary current channel sensor, and apply it to the secondary current channel sensor. adjust only the secondary cu rrent calibrators, so that the same power is computed. table 18. calibration results description value value of calibrator kp = kv*ki = 0.765625 frequency at led f = p*in*vn/3600000 = 40.8889 hz voltage divider sv = (f*dl*vbg 2 )/(fm*vn*in*gv*gi*kp*a i*av*si)= 0,6324mv/v voltage divider resistor r1=r2*(1000/sv-1)
stpm11/12/13/14 schematic 39/45 10 schematic figure 23. charge pump schematic
schematic stpm11/12/13/14 40/45 figure 24. application schematic
stpm11/12/13/14 package mechanical data 41/45 11 package mechanical data in order to meet environmental requirements, st offers these devices in ecopack ? packages. these packages have a lead-free second level interconnect. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com.
package mechanical data stpm11/12/13/14 42/45 dim. mm. inch. min. typ. max. min. typ. max. a 1.2 0.047 a1 0.05 0.15 0.002 0.004 0.006 a2 0. 8 1 1.05 0.0 3 1 0.0 39 0.041 b 0.1 9 0. 3 0 0.007 0.012 c0.0 9 0.20 0.004 0.007 9 d 6.4 6.5 6.6 0.252 0.256 0.260 e 6.2 6.4 6.6 0.244 0.252 0.260 e1 4. 3 4.4 4.4 8 0.16 9 0.17 3 0.176 e 0.65 b s c 0.0256 b s c k0 8 0 8 l 0.45 0.60 0.75 0.01 8 0.024 0.0 3 0 t ss op20 mechanical data c e b a2 a e1 d 1 pin 1 identification a1 l k e 00 8 7225c
stpm11/12/13/14 package mechanical data 43/45 dim. mm. inch. min. typ. max. min. typ. max. a 33 0 12. 99 2 c 12. 8 1 3 .2 0.504 0.51 9 d 20.2 0.7 9 5 n60 2. 3 62 t 22.4 0. 88 2 ao 6. 8 7 0.26 8 0.276 bo 6. 9 7.1 0.272 0.2 8 0 ko 1.7 1. 9 0.067 0.075 po 3 . 9 4.1 0.15 3 0.161 p 11. 9 12.1 0.46 8 0.476 tape & reel t ss op20 mechanical data
revision history stpm11/12/13/14 44/45 12 revision history table 19. document revision history date revision changes 30-jan-2007 1 initial release. 06-feb-2007 2 the figure 11 has been changed. 20-mar-2007 3 general description has been updated. 13-sep-2007 4 add ta bl e 1 in cover page. 21-jan-2008 5 added note: on page 38 .
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